1. Field of the Invention
The invention in general relates to non-volatile electronic memories and more particularly to a memory having a memory cell including a ferroelectric capacitor and a transistor with one electrode of the capacitor connected to the gate of the transistor.
2. Statement of the Problem
It is well-known that ferroelectric materials are capable of retaining a polarization which can be used to store information in a non-volatile memory. An early proposal for a non-volatile ferroelectric device thin could be used to store information was a switch made by placing a ferroelectric crystal across one or more p-n junctions. See U.S. Pat. Nos. 2,791,760 issued to I. M. Ross and 2,791,761 issued to J. A. Moron. In these disclosures, it is proposed that the different polarizations of the ferroelectric material will differently affect the current carried by the junction thus providing a bistable switch that can be used to store information. However, no disclosure of how this device could be incorporated into a memory is provided.
The most common design for non-volatile ferroelectric memories is to simply replace the dielectric material in a conventional DRAM with a ferroelectric material. See for example U.S. Pat. No. 5,038,323 issued to Leonard J. Schwee. Such memories are destructive-read-out (DRO) memories in that the memory state is altered when read. Such memories must be switched each time they are read, which switching tends to cause the memories to fail. Thus, such memories have not yet been commercially successful.
Non-volatile memories which incorporate a ferroelectric material between the gate of a transistor and the semiconducting substrate, sometimes referred to as ferroelectric FETs, have also been proposed. See U.S. Pat. Nos. 3,832,700 issued to Shu-Yau Wu et al., 4,161,038 issued to Shu-Yau Wu, 5,198,994 issued to Kenji Natori, and the article "Ferroelectric FET Device" by P. Arnett, IBM Technical Disclosure Bulletin, Vol. 15, No. 9, Feb. 1973, p. 2825. In the Wu references and some embodiments of the Natori reference the ferroelectric material is deposited directly on a silicon substrate. In some embodiments of the Natori reference and the Arnett reference an insulator is placed between the substrate and the ferroelectric material. Another approach is to sandwich the ferroelectric material between the floating gate and control gate of an EEPROM device. See U.S. Pat. No. 4,888,630 issued to James L. Paterson. However, such devices have remained essentially theoretical possibilities, since they have not been able to retain programmed threshold voltage levels for more than a few minutes, and devices have utility as non-volatile memory elements only if information can be stored for long periods of time. The short retention period for the ferroelectric FET devices is believed to be due to the fact that the transistor configurations inhibit polarization saturation of the ferroelectric layer. Application of a bias between the gate electrode and the substrate establishes different electric fields across the ferroelectric layer, the gate insulating layer (if present), and the channel region of the transistor. The amount of field drop across each layer is inversely proportional to the dielectric constant and thickness of the layer. The highest electric field will develop across the layer with the lowest dielectric constant. Because the dielectric constant of silicon is about 11.7, the dielectric constant of silicon dioxide is about 3.9, and the dielectric constants of most ferroelectrics is greater than 100, most of the field drop occurs across the silicon dioxide and the silicon channel region. Thus, at the 3 volt to 5 volt voltages used in conventional integrated circuits, insufficient field develops across the ferroelectric layer to fully saturate the polarization. With such a weakly polarized ferroelectric, stray fields created in reading the cell and in writing to the cells in the same row and column quickly destroy any memory that exists.
Japanese patent application No. 3-247714 shows a memory cell in which a the gate of a MOS-FET transistor is connected to one side of a ferroelectric capacitor, the word line is connected to the other side of the ferroelectric capacitor, and the bit line is connected between the gate and the capacitor. It is not described how such a memory operates, but since the word line connects directly to the ferroelectric capacitor, the state of polarization of the capacitor will be switched or significantly affected each time the row in which the memory cell is located is addressed. Thus this approach appears to be another essentially theoretical device which cannot long retain a memory state.
3. Solution to the problem
The present invention solves the above problem by providing memory units in which saturated polarization is obtained and in which the state of the cell is not affected by any read or write operations, except the write operation to the particular cell being addressed.
In one embodiment, the invention provides a four-terminal memory unit comprising a ferroelectric capacitor and a transistor with the capacitor connected to the gate of the transistor. In this embodiment the electrodes of the capacitor are conductive layers that are distinct from the gate of the transistor. Two of the terminals are directly connected to the capacitor electrodes and are used to write information into the capacitor. The two others are used to read information from the transistor.
In an implementation of the memory unit according to the invention in an integrated circuit, one plate of the ferroelectric capacitor is formed by the same conductive layer as the gate of the transistor. In another implementation, one electrode of the capacitor is formed by the gate of the transistor and the other electrode is formed by heavily doped portions of the transistor active regions that underlie the gate and ferroelectric layer.
The fact that in each of the above embodiments no low dielectric constant insulating material separates the capacitor electrodes and the ferroelectric material, results in the ability to saturate the polarization of the ferroelectric material with conventional integrated circuit voltages. Further, the highly conducting electrodes that completely, or nearly completely, sandwich the ferroelectric material in each of the embodiments, prevents stray fields in the read process and in writing to other cells from affecting the polarized ferroelectric. Numerous other features, objects and advantages of the invention will become apparent from the following description when read in conjunction with the accompanying drawings.